Fail-safe logical system

ABSTRACT

A fail-safe logical system for performing general logical functions and for generating a predetermined logical output in case of fault of any element of any elemental circuit, wherein an 0-type input unit having an allowable failure-state of 0 and a 1 type input unit having an allowable failure-state of 1, are connected to a fail-safe logical unit which is formed by failsafe logical elemental circuits in accordance with the principle of alternate, cascade circuit arrangement, before and after a NOT circuit, to provide logical elemental circuits having different allowable failure-states.

United States Patent Inventors Appl. No. 725,300 Filed Apr. 30, 1968Patented Jan. 26, 1971 Assignee Kokusai Denshin Denwa Kabuskiki KaishaTokyo-to, Japan a joint-stock company of Japan Priority May 2, 1967, May2, 1967 J p 42/27678 and 42/27679 FAIL-SAFE LOGICAL SYSTEM 5 Claims, 14Drawing Figs.

US. Cl 307/88, 307/204, 328/92 Int. Cl ..H03k 19/162, H031: 19/40 Fieldof Search 328/92, 94;

[56] References Cited UNITED STATES PATENTS 3,015,039 12/ 1961 Morgan307/88 3,122,724 2/1964 Felton et al.. 340/ l 74 3,162,769 12/1964Yamada 307/88 3,016,517 1/1962 Saltzberg.. 307/204X 3,201,701 8/1965Maitra 328/92X 3,226,569 12/1965 James 307/204 3,305,830 2/1967Constantine, Jr... 307/204X 3,421,018 1/1969 Martin 328/92X PrimaryExaminer-Stanley M. Urynowicz, Jr. AttorneysRobert E. Burns and EmmanuelJ. Lobato PATENIEU JAN28 I97! SHEET 1 UF 6 PRIOR ART Fig. 3

. l 1 FAIL-SAFE LOGICAL SYSTEM tion but generates always an allowablelogical output only in a case ofopen or short" fault of any element andal-typed fail-safe logical circuit which performs the prime logicaloperation thereof in the normal condition but generates always anallowable logical output I only in a case of open or short fault of anyelement. At first, a complete fail-safe system using the above-mentionedO-typed-and I-typed failor a control device operating in real time, acontrol device for atomic furnaceor a control device for locomotion, inwhich an extremely high safety standard of devices is required to avoida loss of human life, fail-safe logical systems generating-.apredetermined safe output in case of a fault of any element isnecessary. However, if the logical system comprises binary circuits andif any element in the binary circuit causes a binary fault, such asopen-state or short-state," the logical outputs I and 0 will begenerated under equal probabilities. Acv cordingly, it cannot be clearlyforeseen what output result is obtainedfrom the logical system in a caseof fault. A conventional fail-safe systemhad been proposed to eliminatethe above-mentioned instability of output result in case of fault of iany element. However, since the conventional fail-safe logical system isformed by only logical circuits having an allowable failure-state!)only, they can perform only logical functions restricted within narrowlimits.

An object of this invention is to provide fail-safe logical systemsperfonnable of general logical functions.

Said object and other objects of this invention can be attained by thefail-safe logical system of this invention, characterized in that doublesystems comprising an O-typed input unit having an allowablefailure-state 0 only and an l-typed input unit failed into an allowablefailure-state I only are connected to atleast one fail-safe logical unitwhich is formed-by fail-safe logical .elemental circuits. According tofurther feature of this invention, the fail-safe logical unit is formedunder the principle of alternate, cascade circuit arrangement" in whichbefore and after a NOT circuit, logical circuits having differentallowable failure-states are alternately arranged.

The principle of this invention will be better understood from thefollowing more detailed discussion in conjunction with the accompanyingdrawings, in which I FIG. 1 is a block diagram for illustrating anexample of conventional logical system; 7 FIGS. 2 and 3 are blockdiagrams each for illustrating embodiment of this invention performingthe same function as example shown in-FIG. l;

FIG. 4 is a block diagram for illustrating an example of conventionalsequential circuits;

' FIG. 5 is a block diagram for illustrating an embodiment of thisinvention performing the same function as the example shown in FIG. 4;

' FIG. 6 isa block diagram for describing the constructive principle ofthe system of this invention;

FIG. 7 is'ablock diagram for illustrating an embodiment of safe logicalcircuits will be described. Actual examples of the fail-safe logicalcircuits will next be described. Notations used in the followingdescriptions and drawings are as follows:

V: OR circuit A: AND circuit N: NOT circuit Vi: an i-th O-typed ORcircuit having an allowable failure state 0 only.

V1: an i-th 1-typed OR circuit having an allowable failure state 1 onlyAi: an i-th O-typed AND circuit having an allowable failure state 0 onlyAi: an i-th 1-typed AND circuit having an allowable failure state I onlyNi: an i-th NOT circuit failed into the state 0 Ni: an i-th NOT circuitfailed into the state 1 In the above notations, the numbers i areconsecutively given from the output side. Moreover, references x,, x,,f,- -are input or output variables and references in, -x,,are variableshaving respective allowable failure-states 0 and 1 only.

To make the features of this invention clear, an example of conventionallogical system will first be described with reference to FIG. I. Thisexample is fonned to perform a logical function f x,x, 4. As mentionedhereinbefore, since the logical outputs I and 0 are generated underequal probability if any element in elemental logical circuits causes abinary fault, it cannot be clearly foreseen what output result isobtained from the system in a case of fault.

FIG. 2 shows an embodiment of this invention, which per forms the samefunction as the system shown in FIG. 1 and comprises a 0 only typedinput unit 10 having an allowable failure-state 0, a I only typed inputunit 11 failed into the state 1 and a logical unit U. The input units 10and II are designed so as to perform the same function. Elementallogical circuits are all fail-safe elemental logical circuit describedbelow. Moreover a 0-typed logical circuit "V, and a l-typed logicalcircuit V are arranged alternately in cascade after and before a NOTcircuit N We will hereinafter refer this principle (at least one O-typedlogical circuit and at'least one I-typed logical circuit are arrangedalternately in cascade after and before it NOT circuit for each singlepath from the output terminal to an input terminal) as the principle ofalternate in cascade arrangement." y

The embodiment of FIG. 2 is formed to obtain the output state 0 in acase of fault of any element in the elemental units or circuits l0, ILA-V N and V To obtain this output for illustrating. another example offail-safe parametron ele-' actually obtain a O-typed fail-safe logicalcircuit which performs the prime logical operation thereof in the normalcondistate 0, the OR circuit V comprises a logical circuit Vhaving anallowable failure-state 0 only, the AND circuit A: comprises required tohave'respectively different allowable failure-states I and'0. In a casewhere a plurality of NOT circuits are em ployed to form a logical unit,they are assigned so that different failure-states l and 0 are arrangedalternately before and after each NOT circuit. Moreover, the O-typedinput unit 10 is connected to the O-typed logical circuit A and the I-typed input unit I1 is connected to the I-typed logical circuit V,

As the result of the above formation. the logical output of theembodiment shown in FIG. 2 becomes always the state in a case'of faultof any element in the logical unit U and in the input units and II. Ifrespective failure-states of the elemental circuits V,,A2, N and V, andthe units I0 and 11 are all replaced by different failure-states, theembodiment of FIG. 2 becomes a I-typed logical system.

FIG. 3 shows another embodiment of this invention which are a fail-safedouble logical system. In this embodiment, the O-typed input unit 10 andthe I-typed input unit I1 and the logical unit U are the same as shownin FIG. 2. A logical unit U is designed so as to perform the samelogical function as that of the logical unit "U but to obtain a logicaloutput If in a case of fault of any elemental logical circuits in thislogical unit U. In this logical unit U, the forementioned the principleof alternate in cascade arrangement is adopted before and after a NOTcircuitN uThe input unit 10 and the logical unit U are of O-type and theinput unit 11 and the logical unit U are of l-type. Moreover, acombination of the input unit 10 and the logical unit "U and acombination of the input unit 11 and the logical unit U are designed soas to perform the same logical operation. Accordingly, this embodimentis a complete double system for fail-safe logical operation.

The principle of this invention can be applied to form a failsafesequential circuit.

FIG. 4 shows an example of conventional sequential circuit which is aflip-flop circuit of trigger type. In this example, a delay circuit D,has a delay time equal to the period of input pulses applied from theinput terminal I. When two input pulses of the state I are applied fromthe input terminal I, an output pulse of the state 1 is obtained from anoutput terminal 0.

FIG. 5 shows another embodiment of this invention which is designed toperform the same logical operation as that of the conventional logicalcircuit shown in FIG. 4. In this embodiment, the principle of alternatein cascade arrangement is adopted before and after each of NOT circuits"N, andNt Logical units "U and U perform the same logical operations andare respectively of a O-typed logical circuit and of a I- typed logicalcircuit.

The normal operation of this embodiment will first be described. Ifpulses of the state 1 are simultaneously applied, respectively, to theinput side of the 0-typed logical unit U and the input side of thel-typed logical unit U in a case where flip-flop circuits of units U andU are reset, these pulsive information of the state 1 are passedthrough, respectively, OR circuits "V, and V and circulate in respectiveloops formed by elemental circuits "V A "D, "V, and by elementalcircuits V, a,- D, V, When next pulses of the state 1 are simultaneouslyapplied, respectively, to the input sides of the logical units U and U,a pulse of the state 1 is obtained from each of output terminals 16 and17 since the circulating pulses of the state 1 are respectively appliedto AND circuitsA and A These output pulses of the state 1 aresimultaneously applied, respectively, to NOT circuits N, and "N, andthen applied after NOT, respectively, to AND circuits A;, and A Sincepulses applied from the NOT circuits N, and "N, are of the state 0, boththe outputs of the AND circuits O of references of respective elementalcircuits. If the l-typcd input system and/or the unit U are/is failed,the output of the unit Uassumcs the state I. In a case where one or morefault occurs or occur in each of the logical systems (I0, U) and (11,U), the 0-typed system (10, U) will generate the output of the state 0and the I-typed system (11, U) will generate the output of the, state I.By way of example, if the AND circuit A1 is failed, the output of thisa'AND circuit A1 assumes the state l. Since this pulse of the state I-is applied, after NOT, to the input of the AND circuit A3 the output ofthe AND circuit A, assumes the state 0.-Accordingly, the O-typed logicalsystem and the I-typed logical system-generate respective, ly the outputof the state 0 and the output of the state I. As understood from theabove description,this sequential circuit meets conditions andrequirements for a complete fail-safe logical system.

With reference to FIG. 6, the constructive'principle of a completefail-safe logical system of this invention including the above-mentionedcombination circuits and sequential circuits will be described. Thecomplete fail-safe logical system comprises a 0-typed input unit 10having an allowable failurestate 0 only, a l-typed input unit 11 havingan allowable failure-state 1 only, a O-typed logical unit U having anallowable failure-state 0 only, and a l-typed logical unit U having anallowable failure-state I only. The O-typed input unit 10 and the0-typed logical unit U generate respective normal outputs in the normalcondition while generate always the output 0 only in a case of fault ofany element of their elemental circuits. On the other hand, the l-typedinput unit 11 and the I- typed logical unit u generate normal outputs inthe normal condition while always the output 1 only in a case of faultof any element of their elemental circuits. To realize each of theO-typed units and the l-typed units, the forementioned principle ofalternate in cascade arrangement is applied. In a case where generallogical functions are to be performed, each elemental circuit of thelogical unit U may require the opposite failure-state 1. In such a case,a required failure-state is obtained from a required elemental circuit(e.g.; A, in FIG. 5) of the other logical unit U and applied to therequiring elemental circuit (e.g.; N, in FIG. 5) of the logical unit "U.Such requirement may occur also in the l-typed logical unit U. In thiscase, a required failure-state is obtained from a required elementalcircuit (e.g.; i in FIG. 5) of the logical unit U and applied to arequiring elemental circuit (e.g.; N, in FIG. 5 of the logical unit U.This complete fail-safe logical system comprises double logical systems(10 and U) and (l l and U) which perform the same function and have dualrelationship with respectto the allowable failure-states 0 and I.

With reference to FIG. 7, another embodiment of this invention havingerror detecting function will be described. In this embodiment, theerror detecting circuit is designed so as to have fail-safe function.This embodiment is elementally fonned into double logical systems (U,,,"U, and U,) and (U,,, U, and "U, under the same constructive principleas described with reference to FIG. 6. Error detection is carried out bycomparing outputs of corresponding two units of the two logical systems(U,,, U, and U,) and (U,,, U, and U,) with each other. By way ofexample, the error detecting circuit D, detecting errors of the O-typedlogical unit U, and a l- I typed logical unit U, detects whether or notthe following log- N, andAa assume the state 0 and the pulses of thestate 1 cir- FIG. 5, the input pulse of the unit "U assumes always thestate 0. Accordingly, the output of the unit U assumes the state 0. If.any element of the elemental circuits of the unit U is failed, theoutput of the unit U assumes also the state 0 since all the elementalcircuits are failed into the state 0 as shown in FIG. 5

' ical function is correctly performed:

, If both the two systems generate output state 0 or 1, two

systems operate in the normal condition. Therefore, the logical functionf,,, assumes the value 0., However, if any element of the O-typed unitU, is failed, at least one output of the unit U, assumes the state 0. Onthe contrary, any element of the I- typed unit U, is failed, at leastone output of the unit U, as-

sumes the state 1. Accordingly, the logical function f,,, assumes avalue 1. If the number of outputs is a number n, an error detectingcircuit offail-safe is added to perform the following function withrespect to respective pair of outputs of the Ottyped logical unit andthe l-typed logical unit:

where the notation 2 indicates logical sum. The error detecting circuitD, is an example formed into a I-typed fail-safe circuit generatingalways the output l only in a case of fault of any element therein.

Elemental fail-safe logical circuits employed to form theabove-mentioned complete fail-safe logical systems will now be describedin comparison with conventional elemental logical circuits. r

FIG. 8 shows an example of a conventional parametron element. letsdiscuss conditions of this element in a case of fault of anyconstructive means in comparison with those in the normal condition.This element comprises two magnetic cores M, and M, with nonlinearcharacteristic, an oscillation circuit composed of a capacitor C and anoscillation winding N on the cores M, and M, and tuning with a frequencyL an exciting winding N, for parametrically exciting the oscillationcircuit with a frequency 2!, input windings I,, I and I and an inputtransformer T for applying, to the oscillation circuit, input signalsx,, x, and x, supplied from the input winding I,, I and l The excitingwinding N, has usually one number of turn, and the oscillation windingN, has usually l0 number of turns. The excitation winding N, and theoscillation winding N are wound on the cores M, and M under theprinciple of socalled orthogonal relationship, to avoid direct couplingtherebetween. In case of this illustration, the windings N comprises twocoils connected in opposite senses. A resistor R is employed to couplethe output of this element to a succeeding element. Under theseconstruction, if the excitation current of the frequency gfjs applied tothe excitation winding N, in a case where the input signals x,, x, and xare respectively applied to the input windings I,, I, and l theoscillation circuit generates an oscillation signal with the frequency fand a phase position (0 or 1r) determined in accordance wEh decision bymajority with respect to phase-positions of the input signals.Accordingly, the binary digits 0 and l are represented by thephase-positions 0 and 1r in this parametron element.

If the excitation current stops in this parametron element by way ofexample, the parametric oscillation in the oscillation circuit isstopped. However, if any one of the input signals stops in response tothe breaking of any input winding or the oscillation stop of theimmediately preceding element, this parametron element will receive onlytwo input signals. In this case, if the two input signals have the samephase-position 0 or 1r, this parametron will generates an output signalwith the phase-position 0 or 11-. However, if the two input signals haveopposite phase-positions, this parametron element will havesubstantially no input signal. In this case, this parametron elementgenerates an output signal with a random phase-position (0 or 1r)determined by the initial phase-position of noise. In a logical circuitusing these conventional parametron elements, it is very difficult toknow what element or means is failed since we cannot predetermine thefailure-state (e.g.; the state of the output signal) caused by fault ofany means of the parametron element.

FIG. 9 shows an example of a fail-safe logical circuit to be used in thesystem of this invention. In this example, an even number of inputwindings (I, and 1,) are employed, and a constant winding N is coupledthrough the same apertures of the cores M and M, as the excitationwinding N,. In this case, the constant winding N, and the oscillationwinding N, have opposite senses with respect to the core M, so that theconstant winding N has linear coupling with the oscillation winding Nand has not linear coupling with the excitation winding N,. Moreover, ifit is assumed that the effective intensity of mag netic field applied tothe cores M, and M, by input signals .x, and x, flowing through theinput windings I, and I, is equal to a value I, the intensity ofmagnetic field applied to the cores M, and M, by a constant signal x,flowing through the constant winding N,. is determined so as to belarger or smaller than the value I. The magnetic field applied to thecores M, and M by the constant signal x flowing through the constantwinding N has two possible phase-positions 0,, and 1m. The magneticfields caused by constant signals x having'any of the two possiblephase-positions 0,, and On and having one half or three halves the inputsignals are respectively represented by references 0 0k), 0110A),0,,(3l2jand 011- (3/2). In accordance with the similar notation, themagnetic field applied to the cores M and M by the input signals Jr, andX2 is represented by a reference 0,,(1) or 61r( l If it is assumed thatthe magnetic field 0,,(3/2) is applied to the cores M, and M, by theconstant signal x,.,-the parametron element of FIG. 9 becomes an 0-typedAND circuit having an allowable failure-state 0 only. In other words,this parametron element generates the output signal of the phase Orronly when the input signals x, and x, generate magnetic field 01r( l andthis generates the output of the phase 0,, in other all cases. To makeconditions of this parametron element clear, combinations ofphase-positions and intensities of the input signals x, and x and theoutput signal 2 in cases of normal and failed states are shown in Tablel where references 0,, are assumed as logical digits 1 and 0respectively.

i TABLE 1 Reference Number Operations in normal states:

In this Table l a reference r represents the state of no output signal(nonoscillation From the contents of Table I, it will be understood thatthe 0-typed fail-safe AND circuit having the allowable fail-state 0 onlyperforms its correct operation or, in a case of fail-state of any one ofinput means, excitation means and other constructive means, generates anoutput Z having a phase-position 0,, or becomes no oscillationcondition. In this parametron element, it is assumed that the constantwinding N is not absolutely failed. If this requirement is met in thisparametron element, this element operates in any of combinations shownin Table l in such failure-states as open or short of. the input windingx, or x,, open or short of the excitation winding N,, the crack of theinput cire T, open or short of the winding on the inputcore T, open orshort of the oscillation winding N the crack of the core M, or M,, andopen or short of the capacitor C or the resistor R etc.

FIG. 10 (A) shows another fail-safe parametron element usingmultiaperture core F in accordance with the same principle as mentionedwith reference to FIG. 9. In this example, 7 the core F is providedwith, separately, an aperture h, for

input windings l, and I and two apertures h, for a constantv winding NThe constant winding N is passed through the apertures h, as shown sothat the constant winding N couples directly with the oscillationwinding N, and indirectly (orthogonally) with the excitation winding N,.This element becomes a O-typed fail-safe AND circuit having an allowablefailure-state 0 only if the constant signal x, applied to the constantwinding N, has a phase-position 0,, and an intensity equal to threehalves (3/2) the intensity of input signals x, and x,.

FIG. (B) shows another example of a fail-safe parametron element, inwhich a core T is used to couple input windings I and I, to theoscillation winding N instead of the aperture h, in FIG. 10 (A).

FIG. II shows another example of a fail-safe parametron element using amagnetic wire which is a straight conductor Cu coated with ferromagneticfilm P. In this element, magnetic fields caused by an excitation currentand an oscillation current are intersected with each other at themagnetic wire. The excitation current e,, is applied, together with adirect current from a DC source Ed, through an impedance Z, to thestraight conductor Cu. A constant current e, having a frequency f isapplied, as the constant current x through a relatively large couplingimpedance Z to the straight conductor Cu. Since the oscillation windingN, is helically wound on the magnetic wire so as to have an angle 5 withrespect to the axial direction of the magnetic wire as shown in FIG. 12,the oscillation winding N is coupled with fluxes of the excitationcurrent c and the constant current e; by a component sin eothereof. Thisparametron element meets the conditions for fail-safe, such asoscillation in a predetermined phase-position or non oscillation, in acase of fault of the preceding element or of .the breaking of any ofinput windings I, and 1 In this parametron element, the magnetizationeasy direction of the ferromagnetic film may be established in any ofthe circumference, axial or helical direction of the magnetic wire. Inorder to apply, to the oscillation winding N the magnetic field causedby the constant current e another magnetic wire other than the magneticwire (Cu, P) may be provided so as to be connected to the impedance 2,.

FIG. 13 shows other examples of fail-safe parametron elements in which acommon magnetic field caused by a constant current e, is applied tooscillation windings of a plurality of parametron elements. In thisillustration, the common magnetic field of the constant current e, isapplied through an impedance Z and a loop line L, wound commonly onmagnetic sity of a magnetic field caused by input signals x, and x FIGS.14 (A) and 14 (B) show functional notations of the abovementionedfail-safe AND circuit. In FIG. 14 (A), a notation (M 3/2) represents aparametron element to which a constant current having an intensity (3/2)and a phase-position 0 is applied. References x, and x, represent inputsignals having an intensity (1) and a phase-position 0 or Orr. Areference f shows an outputsignal which has an intensity (I) and aphase-position 0 or Orr in the normal condition. This output signal fhas, in the failure-state of this element, an intensity l and apredetermined phase-position 0., or becomes no signal. Accordingly,since this parametron element receiving the constant current 0,)3/2) isafail-safe AND circuit having the allowable failure-state 0 only,- thiscan be represented by a notationA as shown in FIG. 14 (B). It can bedeemed that the notation "A corresponds to a constant 0,( 3/2).

Table 2 shows fail-safe logical circuits formed by the use of parametronelements in accordance with the above-mentioned principle. In this Table2, significant matters are the intensity and phase-position of theconstant signal. An input signal x indicated in the first lateral linewith respect to a delay circuit having only an allowable failure state 0shows that this notation x indicates that an input signal failed intothe state 1 cannot be connected to this delay circuit. An input signal xindicated in the second lateral line with respect to a delay circuithaving only an allowable failure-state 1 shows similarly that the inputsignal has an allowable failure-state I.

We can understand from contents of the above description that any inputsignal of any fail-safe logical circuit has to have only one allowablefailure-state 0 or 1 to make an entire logical system using thefail-safe logical circuit to give fail-safe function. In this case, aninput signal having only an allowable failure state 0 means no signal ora signal having a phase-position 0 and an intensity l and an inputsignal having only an allowable failure state 1 means a signal having aphase-position 0n and an intensity (I).

TABLE 2 Prime logic Construction Notation 1 Delay circuit having only anallowable failure state 0".

2 Delay circuit having only an allowable failure state 1".

1x lx 3 NOT circuit having only an allowable 1A--|-- x-l failure state0. I

4 NOT circuit having only an allowable xl x-| failure state 1' 5 ANDcircuit having only an allowable x1 0X! failure state "0.

6 AND circuit having only an allowable x1 xi failure state 1".

x2 I he 7 OR circuit having only an allowable xi X1 failure state 0".

8 OR circuit having only an allowable x: x:

failure state 1.

wires W, and W,of the parametron elements so as to intersectprthogonallywith the magnetic wires W and W Effective magnetic fields caused by theconstant current e, and applied to the magnetic wires W and W have anintensity substantially equal to one half (1%) or three halves (3/2) theintensignal which has a phase-position 611- in an only case where boththe input signals x, and x have a phase-position 011. This output signalassumes a phase-position 6 or no signal in other all cases. Moreover,the allowable failure-state of any input signal is the state 0 that isno signal or a signal having the phase position 00.

An AND circuit listed in the sixth lateral line has an output signalwhich has a phase-position, similarly as the AND circuit iysfif hlststeiine. in an on y ase wh both the input signals x and x have a phaseposition 0n. However, the allowable failure-state of any input signal isthe state I that is no signal or a signal having the phase-position 011.This oscillation ph z 1seo f this circuit is determined by the phaseposition 6 of constant current only when the two input signals x and xbecomes simultaneously no signal, so that the output signal in this casehas a phase-position 60. This AND circuit meets requirements for al-typed fail-safe AND circuit having an allowable failure state 1 excepta rare case where two input signals x and x become simultaneously nosignal.

An OR circuit listed in the seventh lateral line has an output signalhaving a phase-position 011' in case where either or both input signal xor/and x has or have a phase-position 6n. These operations meetconditions for an OR circuit. Moreover, if either the input signal x, orx becomes no signal, this OR circuit generates an output signal having aphase-position determined by a remaining input signal. This conditionmeets requirements for a 0-typed OR circuit having an allowablefailure-state 0 only. However, if the two input signals x,

and x become simultaneously no signal; this OR circuit generates anoutput signal having a phase-position 6n determined by the phaseposition 6 of the constant current. Accordingly, this OR circuit meetsrequirements for a O-typed fail-safe OR circuit having an allowablefailure-state 0 except a rare case where two input signals x and xbecome simultaneously no signal. The allowable failure-state of theinput signals x and x is the state 0.

An OR circuit listed in the eighth lateral line has an output signalhaving a phase-position On' either the input signal x or x the inputsignals x and x: has or have a phase-position 611'. Moreover if theinput signal x or x or both the input signals x, and x becomes orsimultaneously become no signal, the output signal has a phase-position011- or becomes no signal These conditions meet requirements for al-typed OR circuit having an allowable failure-state 1 only.

As understoodfromthe above details, the above-mentioned fail-safelogical circuits using parametron elements have a feattgethat means forapplying a seed signal (a constant signal having a predeterminedphase-position 00 or On) to the oscillation circuit of the parametronelement is provided separately from information input means (1 I afeature that the intensity of this seed signal is established betweenintensities (0) and (l) or intensities (l) and (2) in a case of twoinput signals, where it is assumed that the input signal has anintensity Moreover, the phase-position of the seed signal is determinedin accordance with prime logic of the logical circuit. If the number 5of input signals more than two are applied to the logical circuit, theintensity of the seed signal (the constant signal) is establishedbetween intensities (0) and (l) or intensities (I) and (n). As theresult of such construction and conditions, the logical circuit meetsrequirements for a fail-safe logical elemental circuit which generates,in a case of fault of the self circuit or an immediately precedingcircuit, no output signal or an output signal having a predeterminedphase-position. The above-mentioned fail-safe logical circuit meetssubstantially requirements for fail-safe conditions in a case of anyfault of all means except the fault of excitation source.

In the above descriptions, the parametron element is formed by the useof ferromagnetic substance. However, the above-mentioned fail-safelogical circuit can be formed by parametric resonators usingferrodielectric or variacapacity of semiconductor.

We claim:

1. In a fail-safe logical system including a fail-safe logical unitembodying fail-safe logical elemental circuits, wherein said systemgenerates a predetermined logi cal Euififi'ififi failure of any elementof any of said elemental circuits, the improvement comprising:

first input circuit means having a predctennined logical function andhaving means for generating only an 0 output condition upon entry ofsaid first input circuit means into a failure state; and second inputcircuit means, having the same predetermined logical function as saidfirst input circuit means, and having means for generating only a 1output condition upon entry of said second input circuit means into afailurestate and in which said first and second input circuit means areconnected to said fail-safe logical unit.

2. A fail-safe logical system according to claim I, in which the logicalelemental circuits are connected in an alternate, cascade circuitarrangement, wherein at least one of said logical elemental circuitscomprises a NOT circuit, and wherein the logical elemental circuitsconnected respectively to the input and output of each said NOT circuithave opposite I and 0 failure-states.

3. A fail-safe logical system according to claim 1, in which a pair ofsaid logical elemental circuits comprise means for performing the samefunction and have different failure-states 0 and 1, respectively, fromeach other, and in which said logical elemental circuits include errordetecting circuit means connected to said pair of logical elementalcircuits, for detecting whether said pair of circuits have the sameoutput state.

4. A fail-safe logical system according to claim I, in which one of saidfail-safe elemental circuits is a parametron element having input means,and further comprising signal means connected to said parametron elementfor applying a constant signal to said separate oscillationcircuit, theconstant signal having a predetermined phase-position 0 or 1r withrespect to a signal at said input means, and for applying an effectivefield to said parametron having an intensity which differs from thenormal intensity of a field caused by input signals applied to the inputmeans.

5. A fail-safe logical system according to claim 4, in which theconstant signal is commonly applied to a plurality of parametronelements.

1. In a fail-safe logical system including a fail-safe logical unitembodying fail-safe logical elemental circuits, wherein said systemgenerates a predetermined logical output upon failure of any element ofany of said elemental circuits, the improvement comprising: first inputcircuit means having a predetermined logical function and having meansfor generating only an 0 output condition upon entry of said first inputcircuit means into a failure state; and second input circuit means,having the same predetermined logical function as said first inputcircuit means, and having means for generating only a 1 output conditionupon entry of said second input circuit means into a failure-state andin which said first and second input circuit means are connected to saidfail-safe logical unit.
 2. A fail-safe logical system according to claim1, in which the logical elemental circuits are connected in analternate, cascade circuit arrangement, wherein at least one of saidlogical elemental circuits comprises a NOT circuit, and wherein thelogical elemental circuits connected respectively to the input andoutput of each said NOT circuit have opposite 1 and 0 failure-states. 3.A fail-safe logical system according to claim 1, in which a pair of saidlogical elemental circuits comprise means for performing the samefunction and have different failure-states 0 and 1, respectively, fromeach other, and in which said logical elemental circuits include errordetecting circuit means connected to said pair of logical elementalcircuits, for detecting whether said pair of circuits have the sameoutput state.
 4. A fail-safe logical system according to claim 1, inwhich one of said fail-safe elemental circuits is a parametron elementhaving input means, and further comprising signal means connected tosaid parametron element for applying a constant signal to said separateoscillation circuit, the constant signal having a predeterminedphase-position 0 or pi with respect to a signal at said input means, andfor applying an effective field to said parametron having an intensitywhich differs from the normal intensity of a field caused by inputsignals applied to the input means.
 5. A fail-safe logical systemaccording to claim 4, in which the constant signal is commonly appliedto a plurality of parametron elements.